1. Field of the Invention
The present invention relates to non-volatile memory devices. In particular, the present invention relates to the design and the programming of dual-gate flash memory devices.
2. Discussion of the Related Art
In a NAND-type flash memory device, where memory cells in different NAND strings share a common word line, inadvertent programming of unselected memory cells (“program disturb”) must be prevented. Two techniques for preventing such inadvertent programming are self-boosting (SB) and local self-boosting (LSB). Both approaches rely on capacitive coupling to boost the potential in the inversion channel in the unselected memory cell.
The self-boosting technique is described, for example, in (1) “A 3.3 V 32 Mb NAND flash Memory with Incremental Step Pulse Programming Scheme”, by Suh et al., IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995, and (2) U.S. Pat. No. 5,677,873, entitled “Methods of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND Memory Cells Therein”, to Choi et al., filed on Sep. 19, 1996 and issued on Oct. 14, 1997.
The local self-boosting technique is described, for example, in (1) “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, by Jung et al., IEEE J. Solid-State Circuits, vol. 31, pp. 1575-1583, November 1996, (2) U.S. Pat. No. 5,715,194, entitled “Bias Scheme of Program Inhibit for Random Programming in a NAND Flash Memory”, to Hu, filed on Jul. 24, 1996 and issued on Feb. 3, 1998, (3) U.S. Pat. No. 6,011,287, entitled “Non-Volatile Semiconductor Memory Device”, to Itoh et al., filed on Feb. 27, 1998 and issued on Jan. 4, 2000, (4) U.S. Pat. No. 6,061,270, entitled “Method for Programming a Non-Volatile Memory Device with Program Disturb Control”, to Choi, filed on Dec. 28, 1998 and issued on May 9, 2000, and (5) U.S. Pat. No. 6,107,658, entitled “Non-Volatile Semiconductor Memory Device”, to Itoh et al., filed on Dec. 22, 1999 and issued on Aug. 22, 2000.
The methods described in the references mentioned above relate to preventing program disturb in NAND flash memories consisting of floating gate transistors whose inversion channels are located in the bulk of a silicon wafer and whose channel conductivity is controlled by a single control gate at each memory cell.
A NAND flash memory cell with a dual-gate structure is disclosed in U.S. Pat. No. 6,054,734, entitled “Non-Volatile Memory Cell Having Dual Gate Electrodes,” to Aozasa, filed on Nov. 5, 1997 and issued on Apr. 25, 2000. A dual-gate memory cell includes an access device and a storage device, which are located on opposite sides of, and share, an active silicon layer. Aozasa explains that the dual-gate approach reduces read disturb (i.e., program disturb resulting from a read operation) by having close electrical interaction between the devices within a dual-gate structure. In other words, the charge stored in one device in the dual-gate device would affect the threshold voltage of the other device.